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| K6R3024V1D Document Title 128Kx24 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. for AT&T CMOS SRAM Revision History Rev. No. Rev. 0.0 Rev. 0.1 Rev. 0.2 Rev. 0.3 History Design-In Specification Pin Configurations Modified ( page 2 ) Add Timing Diagram page 6 ~ 8 ) Modified Read Cycle Timing(2) 1) Version change from M to D 2) Cin from 20 to 15 pF 3) Icc from 300 to 170mA for 9ns products from 270 to 150mA for 10ns products from 240 to 130mA for 12ns products 4) Isb ( TTL ) from 120 to 40 mA for all products ( CMOS ) from 30 to 15 mA for all products 5) Part number change from -9 to -09 for 9ns products Change write parameter( tDW) from 6ns to 5ns at -10 Final Specification Release Draft Data Dec. 05. 2000 Mar. 07. 2001 April. 04.2001 June. 23.2001 Remark Design-In Preliminary Preliminary Preliminary Rev. 0.4 Rev. 1.0 Oct. 31. 2001 Dec. 19. 2001 Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Revision 1.0 December 2001 K6R3024V1D for AT&T CMOS SRAM 128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES * Fast Access Time 9,10,12ns * Power Dissipation Standby (TTL) : 40mA(Max.) (CMOS) : 15mA(Max.) Operating K6R3024V1D-09 : 170mA(Max.) K6R3024V1D-10 : 150mA(Max.) K6R3024V1D-12 : 130mA(Max.) Single 3.3V Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * 119(7x17)Pin Ball Grid Array Package(14mmx22mm) * Operating in Commercial and Industrial Temperature range. GENERAL DESCRIPTION The K6R3024V1D is a 3,145,728-bit high-speed Static Random Access Memory organized as 131,072 words by 24 bits. The K6R3024V1D uses 24 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG' s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R3024V1D is a three megabit static RAM constructed on an multilayer laminate substrate using three 3.3V, 128K x 8 static RAMS encapsulated in a Ball Grid Array(BGA). PIN FUNCTION Pin Name A0 - A16 WE Pin Function Addresses Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3v) Ground No Connection FUNCTIONAL BLOCK DIAGRAM A0-16 CS1 CS2 CS3 WE OE 17 128K x 8 128K x 8 128K x 8 SRAM SRAM SRAM 8 I/O0-7 8 I/O8-15 8 I/O16-23 CS1,CS2,CS3 OE I/O0 ~ I/O23 VCC Vss NC ORDERING INFORMATION K6R3024V1D-HC09/HC10/HC12 K6R3024V1D-HI09/HI10/HI12 Commercial Temp. Industrial Temp. PIN CONFIGURATIONS(TOP VIEW) K6R3024V1D 1 A B C D E F G H J K L M N P R T U NC NC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O NC NC 2 A A NC VCC Vss VCC Vss VCC Vss VCC Vss VCC Vss VCC NC A A 3 A A CS2 Vss VCC Vss VCC Vss VCC Vss VCC Vss VCC Vss NC A A 4 A CS1 NC Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC WE OE 5 A A CS3 Vss VCC Vss VCC Vss VCC Vss VCC Vss VCC Vss NC A A 6 A A NC VCC Vss VCC Vss VCC Vss VCC Vss VCC Vss VCC NC A A 7 NC NC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O NC NC -2- Revision 1.0 December 2001 K6R3024V1D ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC Pd TSTG TA TA Rating -0.5 to 4.6 -0.5 to 4.6 2 -65 to 150 0 to 70 -40 to 85 for AT&T CMOS SRAM Unit V V W C C C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE CS1 H X X L L L CS2 CS3 X X H L L L OE X X X L X H WE X X X H L H Mode Standby Standby Standby Read Write Outputs Disabled I/O High-Z High-Z High-Z DATAOUT DATAIN High-Z Power Standby Standby Standby Active Active Active X L X H H H RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70C) Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 3.0 2.0 -0.3** Typ 3.3 Max 3.6 VCC+0.3*** 0.8 Unit V V V * The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 8ns) for I 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width 8ns) for I 20mA. -3- Revision 1.0 December 2001 K6R3024V1D Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC VIN=Vss to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH -09 -10 -12 Standby Current ISB -09 -10 -12 ISB1 f=0MHz, CS VCC-0.2V, VINVCC-0.2V or VIN0.2V -09 -10 -12 Output Low Voltage Level Output High Voltage Level VOL VOH IOL=8mA IOH=-4mA Test Conditions for AT&T CMOS SRAM Min 2.4 Max 6 2 170 150 130 40 40 40 15 15 15 0.4 Unit A A mA mA mA mA mA mA mA mA mA V V DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=3.30.3V, unless otherwise specified) * The above parameters are also guaranteed at industrial temperature range. * CS represents CS1 , CS2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3. CAPACITANCE*(TA=25C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance * Capacitance is sampled and not 100% tested Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN - Max 8 15 Unit pF pF AC TEST CONDITIONS*(TA=0 to 70C, Vcc=3.30.3V, unless otherwise specified) Parameter Input Pulse Levels Input Rise and Fall Times Input and output Timing Reference Levels Output Load * The above parameters are also guaranteed at industrial temperature range. Value 0V to 3.0V 3ns 1.5V See Below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ RL = 50 VL = 1.5V DOUT 216 5pF* +3.3V 319 DOUT ZO = 50 30pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance -4- Revision 1.0 December 2001 K6R3024V1D READ CYCLE* Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6R3024V1D-09 Min 9 3 0 0 0 3 0 Max 9 9 4 4 5 9 K6R3024V1D-10 Min 10 3 0 0 0 3 0 Max 10 10 5 5 6 10 for AT&T CMOS SRAM K6R3024V1D-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 7 12 Unit ns ns ns ns ns ns ns ns ns ns ns WRITE CYCLE* Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6R3024V1D-09 Min 9 7 0 7 7 9 0 0 5 0 3 Max 5 K6R3024V1D-10 Min 10 7 0 7 7 9 0 0 5 0 3 Max 5 K6R3024V1D-12 Min 12 8 0 8 8 10 0 0 7 0 3 Max 5 Unit ns ns ns ns ns ns ns ns ns ns ns * This parameter is guaranteed by design but not tested. These specifications are for the individual K6R3024V1D Static RAMs. -5- Revision 1.0 December 2001 K6R3024V1D TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Valid Data tAA for AT&T CMOS SRAM Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tOE OE tOLZ Data out VCC Current ICC ISB tLZ(4,5) tHZ(3,4,5) CS tOHZ Valid Data tPU 50% tPD 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. CS represents CS1 , CS2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3. -6- Revision 1.0 December 2001 K6R3024V1D TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5) for AT&T CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW (10) (9) tWR(5) tWP1(2) tDH -7- Revision 1.0 December 2001 K6R3024V1D TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) for AT&T CMOS SRAM tWR(5) High-Z tLZ tWHZ(6) Data Valid High-Z Data out High-Z High-Z(8) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11. CS represents CS1 , CS2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3. -8- Revision 1.0 December 2001 K6R3024V1D 119 BGA PACKAGE DIMENSIONS 14.000.10 for AT&T CMOS SRAM 1.27 1.27 22.000.10 Indicator of Ball(1A) Location 20.500.10 C1.00 C0.70 0.7500.15 0.600.10 12.500.10 1.50REF 0.600.10 NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX. -9- Revision 1.0 December 2001 |
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